1. Technical Field
This disclosure relates to data conversion, and more particularly to serial to parallel conversion.
2. Description of the Related Art
Systems that employ communication links with serializer-deserializer (SerDes)-based interconnects typically require receiver circuitry to serialize and deserialize the data between serial and parallel data formats. Many systems are now employing serial links to transfer data at speeds in the tens of Gb/sec and beyond. To deserialize the data, a serial-to-parallel converter is used. As shown in FIG. 1, a conventional serial-to-parallel converter uses a significant number of high-speed flip-flop circuits and a corresponding high-speed clock tree to capture the serial data and convert it to parallel data within the device. However, at these speeds, power consumption may be an issue.
More particularly, conventional serial-to-parallel converters may use a number of high-speed flip-flops to capture the serial data and convert it to parallel data using a high-speed clock. An example of such a conventional serial-to-parallel converter is shown in FIG. 1. The serial-to-parallel converter 10 of FIG. 1 receives a serial data stream sdata_in at a pair of one-bit analog-to-digital (A/D) converters (e.g., 11 and 12). The A/D converters 11 and 12 sample the serial data at the clock rate specified by the clock signal clk_in. The A/D 11 captures the serial data on the rising or positive edge of clk_in while the A/D 12 captures the serial data on the falling or negative edge of clk_in. In the embodiment shown in FIG. 1, even data (e.g., bits 0, 2, 4, 6, etc.) is captured on the rising edge and odd data (e.g., bits 1, 3, 5, 7, etc.) is captured on the falling edge of the high-speed clock signal clk_in. Accordingly the flip-flop (FF) 17 captures the even serial data bits that were sampled by the A/D 11 and the FF 18 captures the odd serial data bits that were sampled by the A/D 12 to remove the half-cycle data caused by sampling on the rising and falling edges of clk_in. In addition, each of the FF 19-FF26 captures the respective bits of an eight-bit byte using the buffered (via clock buffer 13) high-speed clock signal clk_in to create an eight-bit parallel data byte. For example, bits zero, two, four, and six may be captured by FFs 19, 20, 21, and 22, respectively, while bits one, three, five, and seven may be captured by FFs 23, 24, 25, and 26, respectively. As shown, the FF19-FF26 are enabled by strobe signals rxen<7:0> only during the time in which the respective data bits should be present. The strobe signals rxen<7:0> are generated by the strobe generator 15 based upon the clk_in signal. Each captured bit passes through a respective exclusive-OR (XOR) gate (e.g., XOR gates 27-34) and when selected the polarity is inverted. The parallel data (e.g., rxdata<7:0>) is then captured by the output flip-flops (e.g., FF 35-FF42) using the slower clock signal clkdiv4, which may be running at one-fourth the frequency of the clk_in signal. The clkdiv4 signal is generated by the clock generator 16, which receives the buffered clk_in signal through clock buffer 14.
The serial-to-parallel converter 10 has many high-speed flip-flops and although only one high-speed clock buffer/driver 13 is shown, it is representative of many such drivers and/or the RC time constants of the wiring in the clock tree that distributes the high-speed clock to the high-speed FF19-FF26. As such, the serial-to-parallel converter 10 of FIG. 1 may consume an unacceptable amount of power at high speeds. Furthermore, it may be desirable to use less overall area when fabricated as an integrated circuit.